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| author | Philippe Mathieu-Daudé | 2021-07-28 13:20:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-08-25 13:02:14 +0200 |
| commit | 5fa38eedbd0b3fad052a11c5efc8031a20ed9b25 (patch) | |
| tree | 171d0fbec457da1b9477706d110f2b6583d36e82 /target/mips/tcg/vr54xx.decode | |
| parent | target/mips: Introduce decodetree structure for NEC Vr54xx extension (diff) | |
| download | qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.tar.gz qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.tar.xz qemu-5fa38eedbd0b3fad052a11c5efc8031a20ed9b25.zip | |
target/mips: Convert Vr54xx MACC* opcodes to decodetree
Convert the following Integer Multiply-Accumulate opcodes:
* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/vr54xx.decode')
| -rw-r--r-- | target/mips/tcg/vr54xx.decode | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index f6b3e42c99..73778f101a 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -6,3 +6,12 @@ # # Reference: VR5432 Microprocessor User’s Manual # (Document Number U13751EU5V0UM00) + +&r rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r + +MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd +MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd +MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd |