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| author | Philippe Mathieu-Daudé | 2021-07-28 13:26:10 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-08-25 13:02:14 +0200 |
| commit | bf7720024c62c9e2707b11aa7fe178be691b2f35 (patch) | |
| tree | 1522a015023d6b3b138ede7f91ec4f715dcdd0d3 /target/mips/tcg/vr54xx.decode | |
| parent | target/mips: Convert Vr54xx MUL* opcodes to decodetree (diff) | |
| download | qemu-bf7720024c62c9e2707b11aa7fe178be691b2f35.tar.gz qemu-bf7720024c62c9e2707b11aa7fe178be691b2f35.tar.xz qemu-bf7720024c62c9e2707b11aa7fe178be691b2f35.zip | |
target/mips: Convert Vr54xx MSA* opcodes to decodetree
Convert the following Integer Multiply-Accumulate opcodes:
* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply, negate, accumulate, and move HI
* MSACHIU Unsigned multiply, negate, accumulate, and move HI
* MSACU Unsigned multiply, negate, accumulate, and move LO
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/vr54xx.decode')
| -rw-r--r-- | target/mips/tcg/vr54xx.decode | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 79bb5175ea..4fc708d80a 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -15,9 +15,13 @@ MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd +MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd +MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd +MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd |