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| author | Alex Bennée | 2020-09-09 13:27:35 +0200 |
|---|---|---|
| committer | Alex Bennée | 2020-09-10 11:43:57 +0200 |
| commit | 102661430cae403ce8cc5768f1a55512c92234be (patch) | |
| tree | cabe6862a8734e24297d647e71e893a10aa14482 /target/mips/translate.c | |
| parent | tests/meson.build: fp tests don't need CONFIG_TCG (diff) | |
| download | qemu-102661430cae403ce8cc5768f1a55512c92234be.tar.gz qemu-102661430cae403ce8cc5768f1a55512c92234be.tar.xz qemu-102661430cae403ce8cc5768f1a55512c92234be.zip | |
target/mips: simplify gen_compute_imm_branch logic
One of the Travis builds was complaining about:
qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
return (TCGCond)(c ^ 1);
../target/mips/translate.c:20031:13: note: ‘cond’ was declared here
TCGCond cond;
Rather than figure out exactly which one was causing the complaint I
just defaulted to TCG_COND_ALWAYS and allowed that state to double up
for the now defunct bcond_compute variable.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200909112742.25730-5-alex.bennee@linaro.org>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 899b90ae0f..398edf7289 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20028,8 +20028,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, int rt, int32_t imm, int32_t offset) { - TCGCond cond; - int bcond_compute = 0; + TCGCond cond = TCG_COND_ALWAYS; TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -20046,7 +20045,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, /* Treat as NOP */ goto out; } else { - bcond_compute = 1; cond = TCG_COND_EQ; } break; @@ -20065,7 +20063,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, tcg_gen_shri_tl(t0, t0, imm); tcg_gen_andi_tl(t0, t0, 1); tcg_gen_movi_tl(t1, 0); - bcond_compute = 1; if (opc == NM_BBEQZC) { cond = TCG_COND_EQ; } else { @@ -20080,7 +20077,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, } else if (rt == 0 && imm != 0) { /* Unconditional branch */ } else { - bcond_compute = 1; cond = TCG_COND_NE; } break; @@ -20088,24 +20084,20 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, if (rt == 0 && imm == 0) { /* Unconditional branch */ } else { - bcond_compute = 1; cond = TCG_COND_GE; } break; case NM_BLTIC: - bcond_compute = 1; cond = TCG_COND_LT; break; case NM_BGEIUC: if (rt == 0 && imm == 0) { /* Unconditional branch */ } else { - bcond_compute = 1; cond = TCG_COND_GEU; } break; case NM_BLTIUC: - bcond_compute = 1; cond = TCG_COND_LTU; break; default: @@ -20118,7 +20110,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, clear_branch_hflags(ctx); ctx->base.is_jmp = DISAS_NORETURN; - if (bcond_compute == 0) { + if (cond == TCG_COND_ALWAYS) { /* Uncoditional compact branch */ gen_goto_tb(ctx, 0, ctx->btarget); } else { |