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| author | Mateja Marjanovic | 2019-04-02 15:43:24 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-05-26 17:33:05 +0200 |
| commit | 41d288582782cf8d63241ecb6efa1e4160fe78f7 (patch) | |
| tree | 5eff3d9ace8a818e0a130087e97f83e1365d5f2e /target/mips/translate.c | |
| parent | target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions (diff) | |
| download | qemu-41d288582782cf8d63241ecb6efa1e4160fe78f7.tar.gz qemu-41d288582782cf8d63241ecb6efa1e4160fe78f7.tar.xz qemu-41d288582782cf8d63241ecb6efa1e4160fe78f7.zip | |
target/mips: Refactor and fix COPY_U.<B|H|W> instructions
The old version of the helper for the COPY_U.<B|H|W> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index c65d19e026..68ea6eefe9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28297,6 +28297,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, generate_exception_end(ctx, EXCP_RI); break; } + if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) && + (df == DF_WORD)) { + generate_exception_end(ctx, EXCP_RI); + break; + } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -28323,7 +28328,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, break; case OPC_COPY_U_df: if (likely(wd != 0)) { - gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_INSERT_df: |