diff options
| author | Aleksandar Markovic | 2019-09-25 14:46:09 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-10-01 16:58:45 +0200 |
| commit | 64a0257f1fc3fd45984b04a4c93d6bfd4cebb97c (patch) | |
| tree | c9eb100b427e2c525c60e31771f0e7cda5c3ee0b /target/mips/translate.c | |
| parent | target/mips: msa: Split helpers for CLT_<S|U>.<B|H|W|D> (diff) | |
| download | qemu-64a0257f1fc3fd45984b04a4c93d6bfd4cebb97c.tar.gz qemu-64a0257f1fc3fd45984b04a4c93d6bfd4cebb97c.tar.xz qemu-64a0257f1fc3fd45984b04a4c93d6bfd4cebb97c.zip | |
target/mips: msa: Split helpers for DIV_<S|U>.<B|H|W|D>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1569415572-19635-18-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 38 |
1 files changed, 32 insertions, 6 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 4db87d637e..27eca0aa3e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28610,6 +28610,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_DIV_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28691,9 +28723,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_DIV_S_df: - gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVL_df: gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); break; @@ -28703,9 +28732,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_DIV_U_df: - gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ILVR_df: gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); break; |