diff options
| author | Aleksandar Markovic | 2019-01-21 14:37:46 +0100 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-01-24 17:48:33 +0100 |
| commit | 8d5388c1de8bf207316369213bd950bafa6badda (patch) | |
| tree | 4a7aa7c102951f9a1e71742a7cbb8023a28c5dcb /target/mips/translate.c | |
| parent | target/mips: Correct the second argument type of cpu_supports_isa() (diff) | |
| download | qemu-8d5388c1de8bf207316369213bd950bafa6badda.tar.gz qemu-8d5388c1de8bf207316369213bd950bafa6badda.tar.xz qemu-8d5388c1de8bf207316369213bd950bafa6badda.zip | |
target/mips: Extend gen_scwp() functionality to support EVA
Extend gen_scwp() functionality to support EVA by adding an
additional argument, modify internals of the function to handle
new functionality, and accordingly change its invocations.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index b362b03d74..aaf7dffdea 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, } static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, - uint32_t reg1, uint32_t reg2) + uint32_t reg1, uint32_t reg2, bool eva) { TCGv taddr = tcg_temp_local_new(); TCGv lladdr = tcg_temp_local_new(); @@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, - ctx->mem_idx, MO_64); + eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); if (reg1 != 0) { tcg_gen_movi_tl(cpu_gpr[reg1], 1); } @@ -21550,7 +21550,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SCWP: check_xnp(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + false); break; } break; @@ -21654,7 +21655,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + true); break; default: generate_exception_end(ctx, EXCP_RI); |