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| author | Aleksandar Markovic | 2018-10-24 18:58:42 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2018-10-25 22:13:33 +0200 |
| commit | ba1e81171fb761aea9a9a4ccadedf808e34eaae2 (patch) | |
| tree | c985b2c07c0cbf7a6b9c89d0c6f83a6871eb581d /target/mips/translate.c | |
| parent | Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in... (diff) | |
| download | qemu-ba1e81171fb761aea9a9a4ccadedf808e34eaae2.tar.gz qemu-ba1e81171fb761aea9a9a4ccadedf808e34eaae2.tar.xz qemu-ba1e81171fb761aea9a9a4ccadedf808e34eaae2.zip | |
target/mips: Add nanoMIPS CRC32 instruction pool
Add nanoMIPS CRC32 instruction pool.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index c44a751be9..4338b9a022 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17475,6 +17475,16 @@ enum { NM_SOV = 0x7a, }; +/* CRC32 instruction pool */ +enum { + NM_CRC32B = 0x00, + NM_CRC32H = 0x01, + NM_CRC32W = 0x02, + NM_CRC32CB = 0x04, + NM_CRC32CH = 0x05, + NM_CRC32CW = 0x06, +}; + /* POOL32A5 instruction pool */ enum { NM_CMP_EQ_PH = 0x00, |