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authorYongbok Kim2018-08-02 16:16:08 +0200
committerAleksandar Markovic2018-08-24 17:51:59 +0200
commitc46562fb2fd41429c7acbf10dedfd5cbe0aa34fa (patch)
treed82f688bf610d81196b067acb05a353434fb5ca6 /target/mips/translate.c
parenttarget/mips: Add emulation of nanoMIPS 16-bit branch instructions (diff)
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target/mips: Add emulation of nanoMIPS 16-bit shift instructions
Add emulation of nanoMIPS 16-bit shift instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/translate.c')
-rw-r--r--target/mips/translate.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b0bbf4cbbd..e3fac1ab0b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16765,6 +16765,21 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P16_MV:
break;
case NM_P16_SHIFT:
+ {
+ int shift = extract32(ctx->opcode, 0, 3);
+ uint32_t opc = 0;
+ shift = (shift == 0) ? 8 : shift;
+
+ switch (extract32(ctx->opcode, 3, 1)) {
+ case NM_SLL16:
+ opc = OPC_SLL;
+ break;
+ case NM_SRL16:
+ opc = OPC_SRL;
+ break;
+ }
+ gen_shift_imm(ctx, opc, rt, rs, shift);
+ }
break;
case NM_P16C:
break;