diff options
| author | Matthew Fortune | 2018-08-02 16:16:20 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2018-08-24 17:51:59 +0200 |
| commit | e222f5067269392af489731221750976d0cf3c05 (patch) | |
| tree | b70b3b0cef619b90c36561db6281fa9c7cf7f6c3 /target/mips/translate.c | |
| parent | target/mips: Add emulation of misc nanoMIPS instructions (p_lsx) (diff) | |
| download | qemu-e222f5067269392af489731221750976d0cf3c05.tar.gz qemu-e222f5067269392af489731221750976d0cf3c05.tar.xz qemu-e222f5067269392af489731221750976d0cf3c05.zip | |
target/mips: Implement emulation of nanoMIPS ROTX instruction
Added a helper for ROTX based on the pseudocode from the
architecture spec. This instraction was not present in previous
MIPS instruction sets.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 0fd77cdb19..5da5dcd779 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -17813,6 +17813,21 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P_ROTX: + if (rt != 0) { + TCGv t0 = tcg_temp_new(); + TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5)); + TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4) + << 1); + TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1)); + + gen_load_gpr(t0, rs); + gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); + tcg_temp_free(t0); + + tcg_temp_free_i32(shift); + tcg_temp_free_i32(shiftx); + tcg_temp_free_i32(stripe); + } break; case NM_P_INS: switch (((ctx->opcode >> 10) & 2) | |