diff options
| author | Aleksandar Markovic | 2019-10-23 12:23:39 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-10-25 18:37:01 +0200 |
| commit | fb5f59b4dca403293921fb1aec45bde935ee51a6 (patch) | |
| tree | 3fb4417785db99f2871a0ac29987bb36b52dff10 /target/mips/translate.c | |
| parent | target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D> (diff) | |
| download | qemu-fb5f59b4dca403293921fb1aec45bde935ee51a6.tar.gz qemu-fb5f59b4dca403293921fb1aec45bde935ee51a6.tar.xz qemu-fb5f59b4dca403293921fb1aec45bde935ee51a6.zip | |
target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1571826227-10583-7-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 76 |
1 files changed, 64 insertions, 12 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 7a35c26062..ea8b8f43a9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28770,6 +28770,70 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); break; @@ -28842,21 +28906,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_ASUB_S_df: gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ILVL_df: - gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_ASUB_U_df: gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ILVR_df: - gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVEV_df: - gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVOD_df: - gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_DOTP_S_df: case OPC_DOTP_U_df: |