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| author | Peter Maydell | 2018-10-19 11:08:31 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-19 11:08:31 +0200 |
| commit | 2ec24af2379e331d062a6fc1cda65bc262c7c17b (patch) | |
| tree | b4c3441d7c3d7e476e97f249e742f35e5619c74e /target/mips/translate_init.inc.c | |
| parent | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2018-10-1... (diff) | |
| parent | target/mips: Add opcodes for nanoMIPS EVA instructions (diff) | |
| download | qemu-2ec24af2379e331d062a6fc1cda65bc262c7c17b.tar.gz qemu-2ec24af2379e331d062a6fc1cda65bc262c7c17b.tar.xz qemu-2ec24af2379e331d062a6fc1cda65bc262c7c17b.zip | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part1-v2' into staging
MIPS queue October 2018, part1, v2
# gpg: Signature made Thu 18 Oct 2018 19:39:00 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-october-2018-part1-v2: (28 commits)
target/mips: Add opcodes for nanoMIPS EVA instructions
target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH
target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>
target/mips: Implement hardware page table walker for MIPS32
target/mips: Add reset state for PWSize and PWField registers
target/mips: Add CP0 PWCtl register
target/mips: Add CP0 PWSize register
target/mips: Add CP0 PWField register
target/mips: Add CP0 PWBase register
target/mips: Add CP0 Config2 to DisasContext
target/mips: Improve DSP R2/R3-related naming
target/mips: Add availability control for DSP R3 ASE
target/mips: Add bit definitions for DSP R3 ASE
target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
target/mips: Increase 'supported ISAs/ASEs' flag holder size
target/mips: Add opcode values of MXU ASE
target/mips: Add organizational chart of MXU ASE
target/mips: Add assembler mnemonics list for MXU ASE
target/mips: Add basic description of MXU ASE
target/mips: Add a comment before each CP0 register section in cpu.h
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/translate_init.inc.c')
| -rw-r--r-- | target/mips/translate_init.inc.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index b3320b9dc7..acab097820 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -320,7 +320,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, .mmu_type = MMU_TYPE_R4000, }, { @@ -485,7 +485,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT, + .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | + ASE_MT, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) @@ -761,7 +762,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - /* A generic CPU providing MIPS64 ASE DSP 2 features. + /* A generic CPU providing MIPS64 DSP R2 ASE features. FIXME: Eventually this should be replaced by a real CPU model. */ .name = "mips64dspr2", .CP0_PRid = 0x00010000, @@ -786,7 +787,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, + .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, .mmu_type = MMU_TYPE_R4000, }, |