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| author | Philippe Mathieu-Daudé | 2021-02-14 17:57:24 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-03-13 23:43:07 +0100 |
| commit | ffc672aa977131ccfccfd0c2aee2b004adb69ed5 (patch) | |
| tree | 3ac66a8b6d606d1599d9488dd9cb258456f2926c /target/mips/tx79.decode | |
| parent | target/mips: Use gen_load_gpr[_hi]() when possible (diff) | |
| download | qemu-ffc672aa977131ccfccfd0c2aee2b004adb69ed5.tar.gz qemu-ffc672aa977131ccfccfd0c2aee2b004adb69ed5.tar.xz qemu-ffc672aa977131ccfccfd0c2aee2b004adb69ed5.zip | |
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tx79.decode')
| -rw-r--r-- | target/mips/tx79.decode | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode new file mode 100644 index 0000000000..2e287ebbf3 --- /dev/null +++ b/target/mips/tx79.decode @@ -0,0 +1,25 @@ +# Toshiba C790's instruction set +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Toshiba Appendix B C790-Specific Instruction Set Details + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rtype rs rt rd sa + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 + +########################################################################### + +MFHI1 011100 0000000000 ..... 00000 010000 @rd +MFLO1 011100 0000000000 ..... 00000 010010 @rd |