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authorAleksandar Markovic2019-07-15 22:00:46 +0200
committerAleksandar Markovic2019-07-15 22:22:05 +0200
commit0d0304f2c4967c892a3216638fc4cb078afa2b44 (patch)
tree03ce3373b6e0769c3b8b3b53fcc1f16778e2edad /target/mips
parenttarget/mips: Add missing 'break' for certain cases of MFTR handling (diff)
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target/mips: Add missing 'break' for certain cases of MTTR handling
This was found by GCC 8.3 static analysis. Fixes: ead9360e2fb Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1563220847-14630-5-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/translate.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b4898d5046..3575eff0ae 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -10055,6 +10055,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
gen_mtc0(ctx, t0, rd, sel);
break;
}
+ break;
case 12:
switch (sel) {
case 0:
@@ -10064,6 +10065,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
gen_mtc0(ctx, t0, rd, sel);
break;
}
+ break;
case 13:
switch (sel) {
case 0: