diff options
| author | Aleksandar Markovic | 2019-08-28 18:26:32 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2019-08-29 11:52:51 +0200 |
| commit | 143a9875e51a358924154ffa76135ca29415dfb5 (patch) | |
| tree | 397f7c9f89dc6c428401b938e2d4641d147bc75c /target/mips | |
| parent | target/mips: Clean up handling of CP0 register 6 (diff) | |
| download | qemu-143a9875e51a358924154ffa76135ca29415dfb5.tar.gz qemu-143a9875e51a358924154ffa76135ca29415dfb5.tar.xz qemu-143a9875e51a358924154ffa76135ca29415dfb5.zip | |
target/mips: Clean up handling of CP0 register 7
Clean up handling of CP0 register 7.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-9-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index a914fe4705..cf2ba5a4a1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7086,7 +7086,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; @@ -7818,7 +7818,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp = DISAS_STOP; @@ -8563,7 +8563,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name = "HWREna"; @@ -9277,7 +9277,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_07: switch (sel) { - case 0: + case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS32R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp = DISAS_STOP; |