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authorRichard Henderson2022-08-11 22:48:03 +0200
committerRichard Henderson2022-09-06 09:04:26 +0200
commit306c872103b4d0986c9f671eb7538b0b70bf69b5 (patch)
tree17360b109ccbc2357188396e082ed033cd13ef9e /target/mips
parentaccel/tcg: Remove translator_ldsw (diff)
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accel/tcg: Add pc and host_pc params to gen_intermediate_code
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/tcg/translate.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index de1511baaf..0d936e2648 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16155,11 +16155,12 @@ static const TranslatorOps mips_tr_ops = {
.disas_log = mips_tr_disas_log,
};
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
+ target_ulong pc, void *host_pc)
{
DisasContext ctx;
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
+ translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base);
}
void mips_tcg_init(void)