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| author | Philippe Mathieu-Daudé | 2021-02-14 18:58:36 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-02-21 19:42:34 +0100 |
| commit | 61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4 (patch) | |
| tree | dc66416876235aee3f5d4767b5bf80b44f4a5950 /target/mips | |
| parent | target/mips: Rename 128-bit upper halve GPR registers (diff) | |
| download | qemu-61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4.tar.gz qemu-61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4.tar.xz qemu-61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4.zip | |
target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-7-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 18 | ||||
| -rw-r--r-- | target/mips/translate.h | 4 |
2 files changed, 22 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 5228e04084..a303c36be3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg) } } +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg == 0) { + tcg_gen_movi_i64(t, 0); + } else { + tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); + } +} + +void gen_store_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg != 0) { + tcg_gen_mov_i64(cpu_gpr_hi[reg], t); + } +} +#endif /* TARGET_MIPS64 */ + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr(int from, int to) { diff --git a/target/mips/translate.h b/target/mips/translate.h index 3014c20cad..468e29d757 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg); +void gen_store_gpr_hi(TCGv_i64 t, int reg); +#endif /* TARGET_MIPS64 */ void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); |