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| author | Philippe Mathieu-Daudé | 2020-10-12 11:57:52 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2020-10-17 11:13:15 +0200 |
| commit | 68b981aa76079216f5765a6aecaf8728f27d3696 (patch) | |
| tree | 51e21fb183ef004f55767fc8c8e57ab72b77dbd3 /target/mips | |
| parent | target/mips: Move cp0_count_ns to CPUMIPSState (diff) | |
| download | qemu-68b981aa76079216f5765a6aecaf8728f27d3696.tar.gz qemu-68b981aa76079216f5765a6aecaf8728f27d3696.tar.xz qemu-68b981aa76079216f5765a6aecaf8728f27d3696.zip | |
target/mips/cpu: Calculate the CP0 timer period using the CPU frequency
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 84b727fefa..46188139b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -144,13 +144,13 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 -#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - env->cp0_count_ns = TIMER_PERIOD_DEFAULT; + env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_DEFAULT, + CPU_FREQ_HZ_DEFAULT); } static void mips_cpu_realizefn(DeviceState *dev, Error **errp) |