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| author | Philippe Mathieu-Daudé | 2020-11-29 23:57:02 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 72f31f60f829980ad22da8049bb41af0dc49c3f4 (patch) | |
| tree | d9a81235b2335628f46381ba6673f8bab35993ef /target/mips | |
| parent | target/mips: Introduce ase_msa_available() helper (diff) | |
| download | qemu-72f31f60f829980ad22da8049bb41af0dc49c3f4.tar.gz qemu-72f31f60f829980ad22da8049bb41af0dc49c3f4.tar.xz qemu-72f31f60f829980ad22da8049bb41af0dc49c3f4.zip | |
target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/cpu-defs.c.inc | 4 | ||||
| -rw-r--r-- | target/mips/cpu.c | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 535d4c0c70..fe0f47aadf 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -978,6 +978,10 @@ static void mvp_init(CPUMIPSState *env) static void msa_reset(CPUMIPSState *env) { + if (!ase_msa_available(env)) { + return; + } + #ifdef CONFIG_USER_ONLY /* MSA access enabled */ env->CP0_Config5 |= 1 << CP0C5_MSAEn; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0643a5784c..001b1b88e2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -532,10 +532,7 @@ static void mips_cpu_reset(DeviceState *dev) env->hflags |= MIPS_HFLAG_M16; } - /* MSA */ - if (ase_msa_available(env)) { - msa_reset(env); - } + msa_reset(env); compute_hflags(env); restore_fp_status(env); |