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| author | Ni Hui | 2022-05-04 04:33:19 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-06-11 11:34:12 +0200 |
| commit | 857816a42b8436021c00d48ab71366aef561be3c (patch) | |
| tree | 68f9ff003c70998b2b7e1ea16ee0225d0e44ca50 /target/mips | |
| parent | target/mips: Do not treat msa INSERT as NOP when wd is zero (diff) | |
| download | qemu-857816a42b8436021c00d48ab71366aef561be3c.tar.gz qemu-857816a42b8436021c00d48ab71366aef561be3c.tar.xz qemu-857816a42b8436021c00d48ab71366aef561be3c.zip | |
target/mips: Fix store adress of high 64bit in helper_msa_st_b()
This patch fix the issue that helper_msa_st_b() write high 64bit
data to where the low 64bit resides, leaving high 64bit undefined.
Fixes: 68ad9260e0 ("target/mips: Use 8-byte memory ops for msa load/store")
Signed-off-by: Ni Hui <shuizhuyuanluo@126.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504023319.12923-1-shuizhuyuanluo@126.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tcg/msa_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 4dde5d639a..736283e2af 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8329,7 +8329,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, /* Store 8 bytes at a time. Vector element ordering makes this LE. */ cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra); + cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); } void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, |