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| author | Philippe Mathieu-Daudé | 2020-12-15 22:40:50 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 878b87b54176d7cea4a74ec544703e408776ed34 (patch) | |
| tree | 0615c5d0a133b96ca03d5b0c27779184ec7ab311 /target/mips | |
| parent | target/mips: Extract MSA translation routines (diff) | |
| download | qemu-878b87b54176d7cea4a74ec544703e408776ed34.tar.gz qemu-878b87b54176d7cea4a74ec544703e408776ed34.tar.xz qemu-878b87b54176d7cea4a74ec544703e408776ed34.zip | |
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-25-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/msa_translate.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index a4f9a6c128..52bd428759 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -304,7 +304,8 @@ static inline int check_msa_access(DisasContext *ctx) return 1; } -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, + TCGCond cond) { /* generates tcg ops to check if any element is 0 */ /* Note this function only works with MSA_WRLEN = 128 */ @@ -339,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) tcg_gen_or_i64(t0, t0, t1); /* if all bits are zero then all elements are not zero */ /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -378,10 +379,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) return true; } - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } + gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; ctx->hflags |= MIPS_HFLAG_BC; |