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| author | Dragan Mladjenovic | 2022-05-04 13:03:58 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-06-11 11:35:34 +0200 |
| commit | 9e4f726d4f489e9f1cd675f4e5ce300f7677ed40 (patch) | |
| tree | 6de37cb8226f1c3445ab247cc807cedf83806797 /target/mips | |
| parent | target/mips: Fix emulation of nanoMIPS MTHLIP instruction (diff) | |
| download | qemu-9e4f726d4f489e9f1cd675f4e5ce300f7677ed40.tar.gz qemu-9e4f726d4f489e9f1cd675f4e5ce300f7677ed40.tar.xz qemu-9e4f726d4f489e9f1cd675f4e5ce300f7677ed40.zip | |
target/mips: Fix emulation of nanoMIPS EXTRV_S.H instruction
The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
nanoMIPS documentation as opcode[20..16]. It is, however, erroneously
considered as opcode[25..21] in the current QEMU implementation. In
function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds
to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and
v0_t is by mistake passed to the helper gen_helper_extr_s_h().
Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h()
to fix this.
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Fixes: 8b3698b294 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-3-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tcg/nanomips_translate.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 58ae35a156..9ee4df2135 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -2036,7 +2036,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, case NM_EXTRV_S_H: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_s_h(t0, t0, v0_t, cpu_env); + gen_helper_extr_s_h(t0, t0, v1_t, cpu_env); gen_store_gpr(t0, ret); break; } |