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| author | Simon Burge | 2021-12-13 14:51:27 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-03-07 20:34:17 +0100 |
| commit | c8aeab3a09b51f828eaa50b994434dbfb3f626b8 (patch) | |
| tree | 5b1cd7d3464d76870f219f22a9048c27120af5ad /target/mips | |
| parent | Merge remote-tracking branch 'remotes/hreitz-gitlab/tags/pull-block-2022-03-0... (diff) | |
| download | qemu-c8aeab3a09b51f828eaa50b994434dbfb3f626b8.tar.gz qemu-c8aeab3a09b51f828eaa50b994434dbfb3f626b8.tar.xz qemu-c8aeab3a09b51f828eaa50b994434dbfb3f626b8.zip | |
target/mips: Fix cycle counter timing calculations
The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c. The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns. Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes of 1.
Signed-off-by: Simon Burge <simonb@NetBSD.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211213135125.18378-1-simonb@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4aae23934b..0766e25693 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -440,8 +440,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; + /* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */ env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock, - cpu->cp0_count_rate); + env->cpu_model->CCRes); assert(env->cp0_count_ns); } |