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| author | Philippe Mathieu-Daudé | 2021-01-28 02:09:18 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-02-21 19:42:34 +0100 |
| commit | ca354f00047a1065a43286debbb8ead0a6d0fe08 (patch) | |
| tree | 1754fac7661fec20c746bebf344e40e405b78b8a /target/mips | |
| parent | target/mips: Let cpu_mips_translate_address() take MMUAccessType arg (diff) | |
| download | qemu-ca354f00047a1065a43286debbb8ead0a6d0fe08.tar.gz qemu-ca354f00047a1065a43286debbb8ead0a6d0fe08.tar.xz qemu-ca354f00047a1065a43286debbb8ead0a6d0fe08.zip | |
target/mips: Let raise_mmu_exception() take MMUAccessType argument
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass
MMUAccessType to raise_mmu_exception(). Let the prototype use it
as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-11-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tlb_helper.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 9bb635885d..0ad2d51b11 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -405,12 +405,12 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) #endif /* !CONFIG_USER_ONLY */ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, - int rw, int tlb_error) + MMUAccessType access_type, int tlb_error) { CPUState *cs = env_cpu(env); int exception = 0, error_code = 0; - if (rw == MMU_INST_FETCH) { + if (access_type == MMU_INST_FETCH) { error_code |= EXCP_INST_NOTAVAIL; } @@ -419,7 +419,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, case TLBRET_BADADDR: /* Reference to kernel address from user mode or supervisor mode */ /* Reference to supervisor address from user mode */ - if (rw == MMU_DATA_STORE) { + if (access_type == MMU_DATA_STORE) { exception = EXCP_AdES; } else { exception = EXCP_AdEL; @@ -427,7 +427,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, break; case TLBRET_NOMATCH: /* No TLB match for a mapped address */ - if (rw == MMU_DATA_STORE) { + if (access_type == MMU_DATA_STORE) { exception = EXCP_TLBS; } else { exception = EXCP_TLBL; @@ -436,7 +436,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, break; case TLBRET_INVALID: /* TLB match with no valid bit */ - if (rw == MMU_DATA_STORE) { + if (access_type == MMU_DATA_STORE) { exception = EXCP_TLBS; } else { exception = EXCP_TLBL; |