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authorDragan Mladjenovic2022-05-04 13:04:01 +0200
committerPhilippe Mathieu-Daudé2022-06-11 11:35:54 +0200
commitdb7596989a67a8f838416f687431f3a0ccb181a0 (patch)
tree32fba89d078745eaab051ba7fbe16c913fa55cd9 /target/mips
parenttarget/mips: Fix emulation of nanoMIPS BNEC[32] instruction (diff)
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target/mips: Fix handling of unaligned memory access for nanoMIPS ISA
nanoMIPS ISA does not support unaligned memory access. Adjust DisasContext's default_tcg_memop_mask to reflect this. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-6-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/tcg/translate.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..5f460fb687 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16023,8 +16023,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
- INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
+ ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
+ (ctx->insn_flags & (ISA_MIPS_R6 |
+ INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
/*
* Execute a branch and its delay slot as a single instruction.