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| author | Richard Henderson | 2022-04-21 17:16:58 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-04-26 17:16:41 +0200 |
| commit | 9d63656354d7cdac6a4b2cafa8243ede4a551a56 (patch) | |
| tree | 253d7eed8ab9975133774b711c1ea36240069a10 /target/nios2/cpu.h | |
| parent | target/nios2: Use hw/registerfields.h for CR_TLBADDR fields (diff) | |
| download | qemu-9d63656354d7cdac6a4b2cafa8243ede4a551a56.tar.gz qemu-9d63656354d7cdac6a4b2cafa8243ede4a551a56.tar.xz qemu-9d63656354d7cdac6a4b2cafa8243ede4a551a56.zip | |
target/nios2: Use hw/registerfields.h for CR_TLBACC fields
Retain the helper macros for single bit fields as aliases to
the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32
instead of manually manipulating the fields.
Since we're rewriting the references to CR_TLBACC_IGN_* anyway,
we correct the name of this field to IG, which is its name in
the official CPU documentation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-28-richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2/cpu.h')
| -rw-r--r-- | target/nios2/cpu.h | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a6811ff7ea..bfa86edd97 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C R_CR_TLBACC_C_MASK +#define CR_TLBACC_R R_CR_TLBACC_R_MASK +#define CR_TLBACC_W R_CR_TLBACC_W_MASK +#define CR_TLBACC_X R_CR_TLBACC_X_MASK +#define CR_TLBACC_G R_CR_TLBACC_G_MASK + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) |