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| author | Tim 'mithro' Ansell | 2017-04-18 08:15:50 +0200 |
|---|---|---|
| committer | Stafford Horne | 2017-04-21 16:55:48 +0200 |
| commit | 356a2db3c6f84e8e79e5afa3913514184bff5f50 (patch) | |
| tree | 08c1c57091a126f8834bb6a06f8971304b28959a /target/openrisc/cpu.c | |
| parent | MAINTAINERS: Add myself as openrisc maintainer (diff) | |
| download | qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.tar.gz qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.tar.xz qemu-356a2db3c6f84e8e79e5afa3913514184bff5f50.zip | |
target/openrisc: Implement EVBAR register
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a216..1524ed981a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj) set_feature(cpu, OPENRISC_FEATURE_OB32S); set_feature(cpu, OPENRISC_FEATURE_OF32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } static void openrisc_any_initfn(Object *obj) @@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); set_feature(cpu, OPENRISC_FEATURE_OB32S); + set_feature(cpu, OPENRISC_FEATURE_EVBAR); } typedef struct OpenRISCCPUInfo { |