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| author | Richard Henderson | 2016-04-05 20:41:48 +0200 |
|---|---|---|
| committer | Richard Henderson | 2017-02-13 22:15:00 +0100 |
| commit | 24c328521b19aff2559118809ddf0522d6dfaaea (patch) | |
| tree | d8bd63c5a682fbc3aeb9d019195059928c482477 /target/openrisc/cpu.h | |
| parent | target/openrisc: Optimize l.jal to next (diff) | |
| download | qemu-24c328521b19aff2559118809ddf0522d6dfaaea.tar.gz qemu-24c328521b19aff2559118809ddf0522d6dfaaea.tar.xz qemu-24c328521b19aff2559118809ddf0522d6dfaaea.zip | |
target/openrisc: Tidy ppc/npc implementation
The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games. Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.
The PPC SPR need not be updated every instruction, merely when we
exit the TB or attempt to read its contents.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 069403884b..82946369dc 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -58,6 +58,7 @@ typedef struct OpenRISCCPUClass { } OpenRISCCPUClass; #define NB_MMU_MODES 3 +#define TARGET_INSN_START_EXTRA_WORDS 1 enum { MMU_NOMMU_IDX = 0, @@ -273,7 +274,6 @@ typedef struct CPUOpenRISCTLBContext { typedef struct CPUOpenRISCState { target_ulong gpr[32]; /* General registers */ target_ulong pc; /* Program counter */ - target_ulong npc; /* Next PC */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ |