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authorPeter Maydell2017-02-14 10:55:48 +0100
committerPeter Maydell2017-02-14 10:55:48 +0100
commit5dae13cd71f0755a1395b5a4cde635b8a6ee3f58 (patch)
treea9e193d020dbfa96afeb2aa9f08442554b415f26 /target/openrisc/exception_helper.c
parentMerge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170213a'... (diff)
parenttarget/openrisc: Optimize for r0 being zero (diff)
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Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into staging
Queued openrisc patches # gpg: Signature made Mon 13 Feb 2017 21:21:03 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-or-20170214: (24 commits) target/openrisc: Optimize for r0 being zero target/openrisc: Tidy handling of delayed branches target/openrisc: Tidy ppc/npc implementation target/openrisc: Optimize l.jal to next target/openrisc: Fix madd target/openrisc: Implement muld, muldu, macu, msbu target/openrisc: Represent MACHI:MACLO as a single unit target/openrisc: Implement msync target/openrisc: Enable trap, csync, msync, psync for user mode target/openrisc: Set flags on helpers target/openrisc: Use movcond where appropriate target/openrisc: Keep SR_CY and SR_OV in a separate variables target/openrisc: Keep SR_F in a separate variable target/openrisc: Invert the decoding in dec_calc target/openrisc: Put SR[OVE] in TB flags target/openrisc: Streamline arithmetic and OVE target/openrisc: Rationalize immediate extraction target/openrisc: Tidy insn dumping target/openrisc: Implement lwa, swa target/openrisc: Fix exception handling status registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/openrisc/exception_helper.c')
-rw-r--r--target/openrisc/exception_helper.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c
index 329a9e400b..a8a5f69b05 100644
--- a/target/openrisc/exception_helper.c
+++ b/target/openrisc/exception_helper.c
@@ -19,7 +19,9 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
#include "exception.h"
void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
@@ -28,3 +30,33 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
raise_exception(cpu, excp);
}
+
+static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc)
+{
+ OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = EXCP_RANGE;
+ cpu_loop_exit_restore(cs, pc);
+}
+
+void HELPER(ove_cy)(CPUOpenRISCState *env)
+{
+ if (env->sr_cy) {
+ do_range(env, GETPC());
+ }
+}
+
+void HELPER(ove_ov)(CPUOpenRISCState *env)
+{
+ if (env->sr_ov < 0) {
+ do_range(env, GETPC());
+ }
+}
+
+void HELPER(ove_cyov)(CPUOpenRISCState *env)
+{
+ if (env->sr_cy || env->sr_ov < 0) {
+ do_range(env, GETPC());
+ }
+}