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| author | Stafford Horne | 2017-08-21 23:37:10 +0200 |
|---|---|---|
| committer | Stafford Horne | 2017-10-20 23:35:47 +0200 |
| commit | 6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87 (patch) | |
| tree | 9f45d3d741dcb0971bf4be0add6250d9deb0a92d /target/openrisc/machine.c | |
| parent | target/openrisc: Make coreid and numcores variable (diff) | |
| download | qemu-6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87.tar.gz qemu-6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87.tar.xz qemu-6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87.zip | |
openrisc/cputimer: Perparation for Multicore
In order to support multicore system we move some of the previously
static state variables into the state of each core.
On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec which has a separate timer counter
per core, but it seems the most simple way to keep each clock in sync.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/machine.c')
| -rw-r--r-- | target/openrisc/machine.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a20cce705d..0a793eb14d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -147,7 +147,6 @@ static const VMStateDescription vmstate_env = { VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), - VMSTATE_UINT32(ttcr, CPUOpenRISCState), VMSTATE_UINT32(picmr, CPUOpenRISCState), VMSTATE_UINT32(picsr, CPUOpenRISCState), |