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| author | Stefan Hajnoczi | 2022-11-01 14:36:13 +0100 |
|---|---|---|
| committer | Stefan Hajnoczi | 2022-11-01 14:36:13 +0100 |
| commit | 18cd31ff30883707408c7d6d952310189903939e (patch) | |
| tree | cf0d18ede8d3bd6d0cf1fe38f4a2ab997df77b6b /target/openrisc/sys_helper.c | |
| parent | Merge tag 'qemu-macppc-20221031' of https://github.com/mcayland/qemu into sta... (diff) | |
| parent | tests/tcg/multiarch: Add munmap-pthread.c (diff) | |
| download | qemu-18cd31ff30883707408c7d6d952310189903939e.tar.gz qemu-18cd31ff30883707408c7d6d952310189903939e.tar.xz qemu-18cd31ff30883707408c7d6d952310189903939e.zip | |
Merge tag 'pull-tcg-20221031-2' of https://gitlab.com/rth7680/qemu into staging
Remove sparc32plus support from tcg/sparc.
target/i386: Use cpu_unwind_state_data for tpr access.
target/i386: Expand eflags updates inline
Complete cpu initialization before registration
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* tag 'pull-tcg-20221031-2' of https://gitlab.com/rth7680/qemu:
tests/tcg/multiarch: Add munmap-pthread.c
accel/tcg: Complete cpu initialization before registration
target/i386: Expand eflags updates inline
accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb
accel/tcg: Remove will_exit argument from cpu_restore_state
target/openrisc: Use cpu_unwind_state_data for mfspr
target/openrisc: Always exit after mtspr npc
target/i386: Use cpu_unwind_state_data for tpr access
accel/tcg: Introduce cpu_unwind_state_data
tcg/tci: fix logic error when registering helpers via FFI
tcg/sparc64: Remove sparc32plus constraints
tcg/sparc64: Rename from tcg/sparc
tcg/sparc: Remove support for sparc32plus
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/openrisc/sys_helper.c')
| -rw-r--r-- | target/openrisc/sys_helper.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 09b3c97d7c..ec145960e3 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -45,14 +45,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(0, 16): /* NPC */ - cpu_restore_state(cs, GETPC(), true); + cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state when "jumping" to the current instruction. */ if (env->pc != rb) { env->pc = rb; env->dflag = 0; - cpu_loop_exit(cs); } + cpu_loop_exit(cs); break; case TO_SPR(0, 17): /* SR */ @@ -131,7 +131,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(8, 0): /* PMR */ env->pmr = rb; if (env->pmr & PMR_DME || env->pmr & PMR_SME) { - cpu_restore_state(cs, GETPC(), true); + cpu_restore_state(cs, GETPC()); env->pc += 4; cs->halted = 1; raise_exception(cpu, EXCP_HALTED); @@ -199,6 +199,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, target_ulong spr) { #ifndef CONFIG_USER_ONLY + uint64_t data[TARGET_INSN_START_WORDS]; MachineState *ms = MACHINE(qdev_get_machine()); OpenRISCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); @@ -232,14 +233,20 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return env->evbar; case TO_SPR(0, 16): /* NPC (equals PC) */ - cpu_restore_state(cs, GETPC(), false); + if (cpu_unwind_state_data(cs, GETPC(), data)) { + return data[0]; + } return env->pc; case TO_SPR(0, 17): /* SR */ return cpu_get_sr(env); case TO_SPR(0, 18): /* PPC */ - cpu_restore_state(cs, GETPC(), false); + if (cpu_unwind_state_data(cs, GETPC(), data)) { + if (data[1] & 2) { + return data[0] - 4; + } + } return env->ppc; case TO_SPR(0, 32): /* EPCR */ |