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| author | Richard Henderson | 2021-03-09 16:52:58 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-12 13:40:10 +0100 |
| commit | 226e6c046c0fce8da32575aad020ca56a5a8064d (patch) | |
| tree | da8f34e3670347fc9eb5e0d25fa8c237a4429e92 /target/openrisc | |
| parent | hw/arm/smmuv3: Uniformize sid traces (diff) | |
| download | qemu-226e6c046c0fce8da32575aad020ca56a5a8064d.tar.gz qemu-226e6c046c0fce8da32575aad020ca56a5a8064d.tar.xz qemu-226e6c046c0fce8da32575aad020ca56a5a8064d.zip | |
target/arm: Fix sve_uzp_p vs odd vector lengths
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix. Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/openrisc')
0 files changed, 0 insertions, 0 deletions