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| author | Peter Maydell | 2020-01-17 14:09:00 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-01-17 14:09:00 +0100 |
| commit | 43ed232fbf65fc594e496b944129a480b2f75b5e (patch) | |
| tree | a8971c0b22066cac018f87e76872ee8d3d5f4818 /target/openrisc | |
| parent | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into staging (diff) | |
| parent | target/openrisc: Fix FPCSR mask to allow setting DZF (diff) | |
| download | qemu-43ed232fbf65fc594e496b944129a480b2f75b5e.tar.gz qemu-43ed232fbf65fc594e496b944129a480b2f75b5e.tar.xz qemu-43ed232fbf65fc594e496b944129a480b2f75b5e.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging
Fix FPSCR masking
# gpg: Signature made Fri 17 Jan 2020 00:51:41 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-or1k-20200116:
target/openrisc: Fix FPCSR mask to allow setting DZF
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/fpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 59e1413279..6f75ea0505 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val) float_round_down }; - env->fpcsr = val & 0x7ff; + env->fpcsr = val & 0xfff; set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status); } |