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| author | Philippe Mathieu-Daudé | 2021-05-17 12:51:31 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-05-27 00:33:59 +0200 |
| commit | 8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3 (patch) | |
| tree | 3605e96525b415e0d739591836978f4d131c5f4a /target/openrisc | |
| parent | cpu: Move AVR target vmsd field from CPUClass to DeviceClass (diff) | |
| download | qemu-8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3.tar.gz qemu-8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3.tar.xz qemu-8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3.zip | |
cpu: Introduce SysemuCPUOps structure
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org>
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46..12d9173043 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,13 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" + +static const struct SysemuCPUOps openrisc_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps openrisc_tcg_ops = { @@ -205,6 +212,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; + cc->sysemu_ops = &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs = 32 + 3; cc->disas_set_info = openrisc_disas_set_info; |