diff options
| author | Laurent Vivier | 2018-01-18 20:38:40 +0100 |
|---|---|---|
| committer | Laurent Vivier | 2018-01-25 16:02:24 +0100 |
| commit | 98670d47cd8d63a529ff230fd39ddaa186156f8c (patch) | |
| tree | ce2092bb342d6350919eb1fbad02dfdd446a4123 /target/openrisc | |
| parent | target/m68k: fix TCG variable double free (diff) | |
| download | qemu-98670d47cd8d63a529ff230fd39ddaa186156f8c.tar.gz qemu-98670d47cd8d63a529ff230fd39ddaa186156f8c.tar.xz qemu-98670d47cd8d63a529ff230fd39ddaa186156f8c.zip | |
accel/tcg: add size paremeter in tlb_fill()
The MC68040 MMU provides the size of the access that
triggers the page fault.
This size is set in the Special Status Word which
is written in the stack frame of the access fault
exception.
So we need the size in m68k_cpu_unassigned_access() and
m68k_cpu_handle_mmu_fault().
To be able to do that, this patch modifies the prototype of
handle_mmu_fault handler, tlb_fill() and probe_write().
do_unassigned_access() already includes a size parameter.
This patch also updates handle_mmu_fault handlers and
tlb_fill() of all targets (only parameter, no code change).
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/cpu.h | 2 | ||||
| -rw-r--r-- | target/openrisc/mmu.c | 8 | ||||
| -rw-r--r-- | target/openrisc/mmu_helper.c | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index cc22dc8871..fb46cc9986 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -356,7 +356,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, +int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index ce2a29dd1a..2bd782f89b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,8 +178,8 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, } #ifndef CONFIG_USER_ONLY -int openrisc_cpu_handle_mmu_fault(CPUState *cs, - vaddr address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; @@ -202,8 +202,8 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, return ret; } #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, - vaddr address, int rw, int mmu_idx) +int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); int ret = 0; diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c index a3e182c42d..97e1d17b5a 100644 --- a/target/openrisc/mmu_helper.c +++ b/target/openrisc/mmu_helper.c @@ -25,12 +25,12 @@ #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { int ret; - ret = openrisc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); + ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); if (ret) { /* Raise Exception. */ |