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| author | Richard Henderson | 2021-07-08 23:34:29 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-07-13 17:13:19 +0200 |
| commit | e0efc48fbc6ed9f308fbbff394c5c1044067909f (patch) | |
| tree | 3dbb3bb1b29b63f8b02c23ea8f0d411aa09bc5a7 /target/openrisc | |
| parent | target/openrisc: Cache constant 0 in DisasContext (diff) | |
| download | qemu-e0efc48fbc6ed9f308fbbff394c5c1044067909f.tar.gz qemu-e0efc48fbc6ed9f308fbbff394c5c1044067909f.tar.xz qemu-e0efc48fbc6ed9f308fbbff394c5c1044067909f.zip | |
target/openrisc: Use dc->zero in gen_add, gen_addc
We still need the t0 temporary for computing overflow,
but we do not need to initialize it to zero first.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/translate.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6aba4c2ffc..059da48475 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -199,10 +199,10 @@ static void gen_ove_cyov(DisasContext *dc) static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); @@ -216,11 +216,11 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); - tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero); + tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |