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| author | Bin Meng | 2021-02-10 03:45:52 +0100 |
|---|---|---|
| committer | David Gibson | 2021-02-10 04:50:11 +0100 |
| commit | 298091f831db1a8f360686369f9760849e90dd03 (patch) | |
| tree | 146281fe319fe57755b884f700356918a01946dd /target/ppc/cpu-models.c | |
| parent | hw/net: fsl_etsec: Reverse the RCTRL.RSF logic (diff) | |
| download | qemu-298091f831db1a8f360686369f9760849e90dd03.tar.gz qemu-298091f831db1a8f360686369f9760849e90dd03.tar.xz qemu-298091f831db1a8f360686369f9760849e90dd03.zip | |
target/ppc: Add E500 L2CSR0 write helper
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.
Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu-models.c')
0 files changed, 0 insertions, 0 deletions