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authorCédric Le Goater2017-03-29 15:53:23 +0200
committerDavid Gibson2017-04-26 04:00:42 +0200
commitad5d1add86b9560c22c3fb8718d6a99eabaaed6a (patch)
tree6d7f4fb0016dc470ff3ce2ae0eae1d59fb726113 /target/ppc/cpu.h
parenttarget/ppc: Add ibm,processor-radix-AP-encodings for TCG (diff)
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ppc/xics: introduce an 'intc' backlink under PowerPCCPU
Today, the ICPState array of the sPAPR machine is indexed with 'cpu_index' of the CPUState. This numbering of CPUs is internal to QEMU and the guest only knows about what is exposed in the device tree, that is the 'cpu_dt_id'. This is why sPAPR uses the helper xics_get_cpu_index_by_dt_id() to do the mapping in a couple of places. To provide a more generic XICS layer, we need to abstract the IRQ 'server' number and remove any assumption made on its nature. It should not be used as a 'cpu_index' for lookups like xics_cpu_setup() and xics_cpu_destroy() do. To reach that goal, we choose to introduce a generic 'intc' backlink under PowerPCCPU, and let the machine core init routine do the ICPState lookup. The resulting object is passed on to xics_cpu_setup() which does the store under PowerPCCPU. The IRQ 'server' number in XICS is now generic. sPAPR uses 'cpu_dt_id' and PowerNV will use 'PIR' number. This also has the benefit of simplifying the sPAPR hcall routines which do not need to do any ICPState lookups anymore. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
-rw-r--r--target/ppc/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cacdd0a750..e0ff0412d6 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1200,6 +1200,7 @@ struct PowerPCCPU {
uint32_t max_compat;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
+ Object *intc;
/* Fields related to migration compatibility hacks */
bool pre_2_8_migration;