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authorDaniel Henrique Barboza2022-03-02 06:51:36 +0100
committerCédric Le Goater2022-03-02 06:51:36 +0100
commitd3412df20a321f2c4d98f5759cef2441206d5bd8 (patch)
treeb8939d6121c3a781872db9ca186f5251e2c4de48 /target/ppc/cpu.h
parenttarget/ppc: add PPC_INTERRUPT_EBB and EBB exceptions (diff)
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target/ppc: trigger PERFM EBBs from power8-pmu.c
This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event. If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/cpu.h')
-rw-r--r--target/ppc/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 79375e8df4..1b687521c7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2502,6 +2502,11 @@ void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
uint32_t error_code, uintptr_t raddr);
+/* PERFM EBB helper*/
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+void raise_ebb_perfm_exception(CPUPPCState *env);
+#endif
+
#if !defined(CONFIG_USER_ONLY)
static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{