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| author | Matheus Ferst | 2021-11-09 20:29:11 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-11-10 08:20:02 +0100 |
| commit | 3620328f787de5190c3c7b0b0041348dc11d796a (patch) | |
| tree | 5efb0871f076529036cc0021fabfb2ad9f7874b8 /target/ppc/translate/fp-impl.c.inc | |
| parent | Update version for v6.2.0-rc0 release (diff) | |
| download | qemu-3620328f787de5190c3c7b0b0041348dc11d796a.tar.gz qemu-3620328f787de5190c3c7b0b0041348dc11d796a.tar.xz qemu-3620328f787de5190c3c7b0b0041348dc11d796a.zip | |
target/ppc: Fix register update on lf[sd]u[x]/stf[sd]u[x]
These instructions should update the GPR indicated by the field RA
instead of RT. This error caused a regression on Mac OS 9 boot and some
graphical glitches in OS X.
Fixes: a39a106634a9 ("target/ppc: Move load and store floating point instructions to decodetree")
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/translate/fp-impl.c.inc')
| -rw-r--r-- | target/ppc/translate/fp-impl.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index d1dbb1b96b..c9e05201d9 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -1328,7 +1328,7 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ, set_fpr(rt, t0); } if (update) { - tcg_gen_mov_tl(cpu_gpr[rt], ea); + tcg_gen_mov_tl(cpu_gpr[ra], ea); } tcg_temp_free_i64(t0); tcg_temp_free(ea); |