diff options
| author | Jose Ricardo Ziviani | 2017-01-10 03:10:10 +0100 |
|---|---|---|
| committer | David Gibson | 2017-01-31 00:10:14 +0100 |
| commit | e04797f79e48b5410457ec093249676585361de0 (patch) | |
| tree | a8a0cf7065068ecb6f991144a7fb515850c32422 /target/ppc/translate | |
| parent | host-utils: Implement unsigned quadword left/right shift and unit tests (diff) | |
| download | qemu-e04797f79e48b5410457ec093249676585361de0.tar.gz qemu-e04797f79e48b5410457ec093249676585361de0.tar.xz qemu-e04797f79e48b5410457ec093249676585361de0.zip | |
ppc: Implement bcds. instruction
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate')
| -rw-r--r-- | target/ppc/translate/vmx-impl.inc.c | 3 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-ops.inc.c | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index e8e527fe69..84ebb7e020 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -1016,6 +1016,7 @@ GEN_BCD2(bcdcfsq) GEN_BCD2(bcdctsq) GEN_BCD2(bcdsetsgn) GEN_BCD(bcdcpsgn); +GEN_BCD(bcds); static void gen_xpnd04_1(DisasContext *ctx) { @@ -1090,6 +1091,8 @@ GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ bcdsub, PPC_NONE, PPC2_ALTIVEC_207) GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ bcdcpsgn, PPC_NONE, PPC2_ISA300) +GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ + bcds, PPC_NONE, PPC2_ISA300) static void gen_vsbox(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index 57dce6e465..7b4b0096d6 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -62,7 +62,8 @@ GEN_VXFORM_207(vaddudm, 0, 3), GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vsubuwm, 0, 18), -GEN_VXFORM_207(vsubudm, 0, 19), +GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), +GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM(vmaxub, 1, 0), GEN_VXFORM(vmaxuh, 1, 1), GEN_VXFORM(vmaxuw, 1, 2), |