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| author | Leandro Lupori | 2022-07-12 21:37:41 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza | 2022-07-18 18:59:43 +0200 |
| commit | e7beaea55bd1efcb554b8e021092a2e79a317b61 (patch) | |
| tree | ecb27392b085b4dcca6f4d4584273d4714a128f2 /target/ppc/translate | |
| parent | target/ppc: Move tlbie[l] to decode tree (diff) | |
| download | qemu-e7beaea55bd1efcb554b8e021092a2e79a317b61.tar.gz qemu-e7beaea55bd1efcb554b8e021092a2e79a317b61.tar.xz qemu-e7beaea55bd1efcb554b8e021092a2e79a317b61.zip | |
target/ppc: Implement ISA 3.00 tlbie[l]
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220712193741.59134-3-leandro.lupori@eldorado.org.br>
[danielhb: moved 'set' declaration to TLBIE_RIC_PWC block]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/translate')
| -rw-r--r-- | target/ppc/translate/storage-ctrl-impl.c.inc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc index 7793297dd4..467c390888 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -21,6 +21,8 @@ * Store Control Instructions */ +#include "mmu-book3s-v3.h" + static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) { #if defined(CONFIG_USER_ONLY) @@ -65,6 +67,21 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local) tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); gen_helper_tlbie(cpu_env, t0); tcg_temp_free(t0); + +#if defined(TARGET_PPC64) + /* + * ISA 3.1B says that MSR SF must be 1 when this instruction is executed; + * otherwise the results are undefined. + */ + } else if (a->r) { + gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs], + tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT | + a->prs << TLBIE_F_PRS_SHIFT | + a->r << TLBIE_F_R_SHIFT | + local << TLBIE_F_LOCAL_SHIFT)); + return true; +#endif + } else { gen_helper_tlbie(cpu_env, cpu_gpr[rb]); } |