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| author | Nikunj A Dadhania | 2017-02-27 05:57:54 +0100 |
|---|---|---|
| committer | David Gibson | 2017-03-01 01:23:39 +0100 |
| commit | dd09c36159858c66ab6e47c688e4177dd3912bf0 (patch) | |
| tree | 1f48513b6d6035239103c89b4d5d22a13b5335e1 /target/ppc/translate_init.c | |
| parent | target/ppc: Correct SDR1 masking (diff) | |
| download | qemu-dd09c36159858c66ab6e47c688e4177dd3912bf0.tar.gz qemu-dd09c36159858c66ab6e47c688e4177dd3912bf0.tar.xz qemu-dd09c36159858c66ab6e47c688e4177dd3912bf0.zip | |
target/ppc: support for 32-bit carry and overflow
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
addze, and subfze always updates CA and CA32.
=> CA reflects the carry out of bit 0 in 64-bit mode and out of
bit 32 in 32-bit mode.
=> CA32 reflects the carry out of bit 32 independent of the
mode.
=> SO and OV reflects overflow of the 64-bit result in 64-bit
mode and overflow of the low-order 32-bit result in 32-bit
mode
=> OV32 reflects overflow of the low-order 32-bit independent of
the mode
* Multiply Low and Divide:
For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
reflects overflow of the 64-bit result
For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
reflects overflow of the 32-bit result
* Negate with OE=1 (nego)
For 64-bit mode if the register RA contains
0x8000_0000_0000_0000, OV and OV32 are set to 1.
For 32-bit mode if the register RA contains 0x8000_0000, OV and
OV32 are set to 1.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate_init.c')
| -rw-r--r-- | target/ppc/translate_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index c92435d910..4dd1e36a55 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -107,7 +107,7 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) /* XER */ static void spr_read_xer (DisasContext *ctx, int gprn, int sprn) { - gen_read_xer(cpu_gpr[gprn]); + gen_read_xer(ctx, cpu_gpr[gprn]); } static void spr_write_xer (DisasContext *ctx, int sprn, int gprn) |