diff options
| author | Matheus Ferst | 2021-06-01 21:35:27 +0200 |
|---|---|---|
| committer | David Gibson | 2021-06-03 10:10:31 +0200 |
| commit | e7a5d578f7c39d54efe1cf1695f85c57354b0191 (patch) | |
| tree | a90ee20a5056e97ba32306c40ff914610984c894 /target/ppc | |
| parent | target/ppc: Implement vcfuged instruction (diff) | |
| download | qemu-e7a5d578f7c39d54efe1cf1695f85c57354b0191.tar.gz qemu-e7a5d578f7c39d54efe1cf1695f85c57354b0191.tar.xz qemu-e7a5d578f7c39d54efe1cf1695f85c57354b0191.zip | |
target/ppc: Move addpcis to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/insn32.decode | 6 | ||||
| -rw-r--r-- | target/ppc/translate.c | 9 | ||||
| -rw-r--r-- | target/ppc/translate/fixedpoint-impl.c.inc | 7 |
3 files changed, 13 insertions, 9 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 77edf407ab..93e5d44d9e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -23,6 +23,10 @@ %ds_si 2:s14 !function=times_4 @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si +&DX rt d +%dx_d 6:s10 16:5 0:1 +@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d + &VX vrt vra vrb @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX @@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D +ADDPCIS 010011 ..... ..... .......... 00010 . @DX + ## Fixed-Point Logical Instructions CFUGED 011111 ..... ..... ..... 0011011100 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ed5515f8e2..35d8831d44 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1779,14 +1779,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } -/* addpcis */ -static void gen_addpcis(DisasContext *ctx) -{ - target_long d = DX(ctx->opcode); - - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); -} - static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, int sign, int compute_ov) { @@ -7659,7 +7651,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 50933a3b9d..2713366791 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a) return trans_ADDI(ctx, a); } +static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16)); + return true; +} + static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a) { gen_invalid(ctx); |