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| author | Nicholas Piggin | 2022-05-19 15:59:05 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza | 2022-05-26 22:11:33 +0200 |
| commit | fcb830af30adaef6219f6b712f24ec3e794cf2c8 (patch) | |
| tree | 9abdd79f73e2c276574e49f6a04865667c11acff /target/ppc | |
| parent | target/ppc: declare vmsumsh[ms] helper with call flags (diff) | |
| download | qemu-fcb830af30adaef6219f6b712f24ec3e794cf2c8.tar.gz qemu-fcb830af30adaef6219f6b712f24ec3e794cf2c8.tar.xz qemu-fcb830af30adaef6219f6b712f24ec3e794cf2c8.zip | |
target/ppc: Fix eieio memory ordering semantics
The generated eieio memory ordering semantics do not match the
instruction definition in the architecture. Add a big comment to
explain this strange instruction and correct the memory ordering
behaviour.
Signed-off: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/translate.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fa34f81c30..eb42f7e459 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3513,7 +3513,32 @@ static void gen_stswx(DisasContext *ctx) /* eieio */ static void gen_eieio(DisasContext *ctx) { - TCGBar bar = TCG_MO_LD_ST; + TCGBar bar = TCG_MO_ALL; + + /* + * eieio has complex semanitcs. It provides memory ordering between + * operations in the set: + * - loads from CI memory. + * - stores to CI memory. + * - stores to WT memory. + * + * It separately also orders memory for operations in the set: + * - stores to cacheble memory. + * + * It also serializes instructions: + * - dcbt and dcbst. + * + * It separately serializes: + * - tlbie and tlbsync. + * + * And separately serializes: + * - slbieg, slbiag, and slbsync. + * + * The end result is that CI memory ordering requires TCG_MO_ALL + * and it is not possible to special-case more relaxed ordering for + * cacheable accesses. TCG_BAR_SC is required to provide this + * serialization. + */ /* * POWER9 has a eieio instruction variant using bit 6 as a hint to |