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| author | Jonathan Behrens | 2019-05-08 00:36:46 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:25 +0200 |
| commit | 087b051a51a0c2a5bc1e8d435a484a8896b4176b (patch) | |
| tree | 1601ee3643102d79f17f561e2a18e3be81f191e3 /target/riscv/Makefile.objs | |
| parent | target/riscv: Add checks for several RVC reserved operands (diff) | |
| download | qemu-087b051a51a0c2a5bc1e8d435a484a8896b4176b.tar.gz qemu-087b051a51a0c2a5bc1e8d435a484a8896b4176b.tar.xz qemu-087b051a51a0c2a5bc1e8d435a484a8896b4176b.zip | |
target/riscv: More accurate handling of `sip` CSR
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/Makefile.objs')
0 files changed, 0 insertions, 0 deletions