diff options
| author | Alistair Francis | 2020-02-01 02:03:05 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2020-02-27 22:46:32 +0100 |
| commit | 551fa7e8a695ea5fd1cca8ffd318556855bbf54f (patch) | |
| tree | bacda76c80d5355e320e34e38883d54e902cb7b2 /target/riscv/cpu.c | |
| parent | target/riscv: Set htval and mtval2 on execptions (diff) | |
| download | qemu-551fa7e8a695ea5fd1cca8ffd318556855bbf54f.tar.gz qemu-551fa7e8a695ea5fd1cca8ffd318556855bbf54f.tar.xz qemu-551fa7e8a695ea5fd1cca8ffd318556855bbf54f.zip | |
target/riscv: Add support for the 32-bit MSTATUSH CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 44ad768a84..b27066f6a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -237,6 +237,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); +#ifdef TARGET_RISCV32 + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); +#endif if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); |