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| author | Frank Chang | 2021-12-10 08:43:26 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | 2d258b428b4f61b71be823fe2a67e7a174078501 (patch) | |
| tree | 9018a7ff8fe046a1c319e490de4a4e06012fb975 /target/riscv/cpu.h | |
| parent | target/riscv: zfh: add Zfh cpu property (diff) | |
| download | qemu-2d258b428b4f61b71be823fe2a67e7a174078501.tar.gz qemu-2d258b428b4f61b71be823fe2a67e7a174078501.tar.xz qemu-2d258b428b4f61b71be823fe2a67e7a174078501.zip | |
target/riscv: zfh: implement zfhmin extension
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h, fcvt.h.d
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 570c49f365..ef677f9092 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -313,6 +313,7 @@ struct RISCVCPU { bool ext_ifencei; bool ext_icsr; bool ext_zfh; + bool ext_zfhmin; char *priv_spec; char *user_spec; |