diff options
| author | Frank Chang | 2022-01-18 02:45:14 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:56 +0100 |
| commit | 32e579b8c510f0c8d7023d87b0cfacf782cb4a62 (patch) | |
| tree | ff7e162e9591c021e7583c05afea7c30e63ea611 /target/riscv/cpu.h | |
| parent | target/riscv: rvv-1.0: Allow Zve64f extension to be turned on (diff) | |
| download | qemu-32e579b8c510f0c8d7023d87b0cfacf782cb4a62.tar.gz qemu-32e579b8c510f0c8d7023d87b0cfacf782cb4a62.tar.xz qemu-32e579b8c510f0c8d7023d87b0cfacf782cb4a62.zip | |
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 424bdcc7fa..03552f4aaa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -340,6 +340,7 @@ struct RISCVCPU { bool ext_icsr; bool ext_zfh; bool ext_zfhmin; + bool ext_zve32f; bool ext_zve64f; char *priv_spec; |