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authorLIU Zhiwei2022-01-20 13:20:44 +0100
committerAlistair Francis2022-01-21 06:52:57 +0100
commiteef11ce325f1544ca0cafb1c734cdb8b1d0cb123 (patch)
tree88e42444b415eee0e52fd290a56c54181c931ef5 /target/riscv/cpu.h
parenttarget/riscv: Adjust vsetvl according to XLEN (diff)
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target/riscv: Remove VILL field in VTYPE
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe58ccaeae..55635d68d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,7 +111,6 @@ FIELD(VTYPE, VTA, 6, 1)
FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
-FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];