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| author | Alistair Francis | 2021-04-24 05:33:31 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:07 +0200 |
| commit | 419ddf00ed78c7f695a9d318cd8fbcab78b7bede (patch) | |
| tree | 5ba1d5da14dccec6ffcef215b381acd532eae840 /target/riscv/cpu_bits.h | |
| parent | target/riscv: Remove the hardcoded MSTATUS_SD macro (diff) | |
| download | qemu-419ddf00ed78c7f695a9d318cd8fbcab78b7bede.tar.gz qemu-419ddf00ed78c7f695a9d318cd8fbcab78b7bede.tar.xz qemu-419ddf00ed78c7f695a9d318cd8fbcab78b7bede.zip | |
target/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6e30b312f0..d98f3bc8bc 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,17 +432,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL -#if defined(TARGET_RISCV32) -#define SATP_MODE SATP32_MODE -#define SATP_ASID SATP32_ASID -#define SATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define SATP_MODE SATP64_MODE -#define SATP_ASID SATP64_ASID -#define SATP_PPN SATP64_PPN -#endif - /* VM modes (mstatus.vm) privileged ISA 1.9.1 */ #define VM_1_09_MBARE 0 #define VM_1_09_MBB 1 |